Hardware

Arithmetic Logic Unit

Adder Module
Logic Module

The main part of the ALU consists of the modules shown above. The adder module provides 2's complement addition of the operand registers, i.e. the second operand can be optionally bit-wise inverted before adding. A carry is generated that can be stored in the status word and the current carry from the status word is used for addition with carry.

The adder module is thus used for the following purposes:

The picture on the right displays the generic bit wise logic module. A 74HC08 can be plugged in to implement a bit-wise AND. If a pin-compatible 74HC32 is used, the module provides a bit-wise OR. Similarly, a 74HC86 is used for bit-wise XOR. The bus address can be configured with a jumper on the bottom, to allow the same PCB design to be used for all of those.

Shift Module

An additional shift register module is provided. It mainly implements right shift and right rotate through carry which can not otherwise be done by the adder. It also implements byte swapping for convenience, i.e. exchanging the lower and the upper 8 bit in a single operation.

Due to PCB space constraints, it implements the carry decoding (selecting either shift out or adder carry out) and the zero detection (determining if the current bus word is zero) for the status word module.

Status Register

Status Word Module

The status word uses three 74HC74 dual flip flops to store 6 flags: carry, zero, sign, interrupt enable, user mode and mmu enable.

The first four flags can be individually set or cleared for convenience (done by a 74HC138). The entire status word can be written onto the bus or read from the bus.

The first three flags can be updated with results from the ALU modules and are used as inputs to the ALU modules.

The user mode flag can be set to disable certain parts of the processor. If it is set, only the first three flags of the status word can be changed.

Both the user mode and MMU enable flags are connected to an external memory & I/O bus. An external address translation logic can than determine if and how to translate memory addresses and if a special protection fault interrupt signal should be generated.

The control logic can temporarily override the carry (force to zero or one) and the user mode flag (force to zero).

Register File

Register File Module

The register file contains eight 16 bit registers. Two 74HC138 decoders are used for decoding read and write addresses.

The register file PCB design is used twice in the processor. Once for general purpose registers (with R7 used as program counter) and once for control registers and constants.

Jumpers can be used to configure the coresponding bus address. The constant/control register module also has its write line disabled if the user mode flag is set (also configured through jumpers).

The previous prototype had a hardwired diode matrix with constant values. Reusing the register module for constants allows both reusing existing, spare PCBs, allows for more flexible design changes and gives an operating system the ability to freely set things like the interrupt handler address.

On the down side, it requires more memory ICs and the computer operator has to set some of the constants during system initialization.

Input/Output Module

I/O Module

The I/O module (still in production, inter dependency issues with front panel design) connects the processor internal bus to an external machine bus. Address and data are demultiplexed for the external bus and Z80 style control signals are generated, including M1, MMU enable and user mode for use by an external memory management unit.

The module also contains some circuitry for overriding the MMU enable line (temporarily force off) and interface circuitry for the front panel.

Control Logic

The control logic contains big EPROMs (probably two 27C4002) with micro code on them.

For decoding instructions, the current opcode, used mode flag, interrupt, fault lines and a counter are connected to the address bus of the ROMs.

During a machine clock cycle, the counter is incremented on the falling edge, the output of the ROMs is allowed to stabilize and are latched on the rising edge into multiple 74HC574 connected to the control lines thus minimizing the possibility of glitches on the control lines, especially when a new opcode is latched on the input (together with a simultaneous reset of the counter).

The control logic can be temporarily disabled through a front panel switch and put into a high-impedance state to allow manual control of the machine over the front panel. Similarly, the system clock can be switched to either an internal crystal oscillator or a single step button on the front panel.

Back Plane Bus

The current version of the processor is internally built on a 64 pin DIN41612 back plane bus. The previous prototype used a split control & data bus with one ribbon cable each and had the processor split into a high-half and a low-half, connected by a single module that attached to all four cables (it was cheap but turned out quite messy).

The unified bus OMNIBUS contains data & address lines, control lines and supply voltage. The pin out of the male PCB connector is as follows:

       33   1
    VCC o   o VCC
     D0 o   o
     D1 o   o
     D2 o   o
     D3 o   o
     D4 o   o
     D5 o   o
     D6 o   o
     D7 o   o
     D8 o   o M1
     D9 o   o MMUOV
    D10 o   o UCF
    D11 o   o ULF
    D12 o   o PSWR
    D13 o   o PSEL
    D14 o   o CLU
    D15 o   o UOV
     A0 o   o COV
     A1 o   o CINH
     A2 o   o TPW
     A3 o   o SIGN
     A4 o   o IEN
     B2 o   o MEMW
     B1 o   o ZERO
     B0 o   o NZERO
    CIN o   o MMU
   COUT o   o USR
   AINV o   o PF
   REGW o   o INT
    BWR o   o WC
    AWR o   o SOUT
    GND o   o GND
       64   32

The female connector on the back plane has the sides flipped.

Apart from the 16 bit data bus (D0...D15), there are 8 address lines on the bus, 5 bit for source select lines (A0...A4) and 3 bit for destination select (B0...B2).

The source address determines what module output to write onto the bus:

The destination address is used by the register and control register module as destination register address and by the status word module for addressing bits.

Front Panel

Front Panel

The front panel is simply an A3 sized board with switches that allow overriding the internal data and control lines of the processor.

For convenience, the contents of the A and B operands, as well as the current instruction word are displayed by rows of LEDs.

In the current prototype, the front panel is made out of wood with hand drilled holes and writing on it. The next version of the front panel is based on the picture above. Plans are to make the front panel itself out of smaller panels that are mounted onto two rails for rapid prototyping/testing. The holes will most likely be cut and the writing engraved in wood by a laser cutter.

The final version of the panels will most likely be made out of stainless steel with labels produced by a vinyl cutting plotter.